This invention relates to programmable logic integrated circuit devices, and more particularly to the organization and interconnection of the regions of programmable logic on such devices.
Cliff et al. U.S. patent application Ser. No. 08/672,676, filed Jun. 28, 1996 (which is hereby incorporated by reference herein in its entirety) shows programmable logic devices having regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each region includes a plurality of subregions of programmable logic. Each subregion is programmable to perform a relatively elementary logic function (e.g., form any logical combination of four input signals applied to the subregion and produce output signals which are the combinatorial signal, the combinatorial signal registered by the subregion, or both the combinatorial and registered signals). Interconnection conductors are provided for programmably interconnecting the inputs and outputs of the subregions. For example, these interconnection conductors may include horizontal conductors extending along each row of regions, vertical conductors extending along each column of regions, and local conductors associated with the regions for bringing signals into the associated regions, conveying signals out of the associated regions, and making local interconnections among the subregions in the associated regions.
For the most part, programmable logic devices are designed as general-purpose devices. This means that the designer of the device does not know all the uses to which the device may be put. For example, the designer does not know precisely how many of various types of interconnection resources to provide in order to ensure that most potential users of the device can make all needed interconnections, without providing such an excess of such resources that large amounts of those resources are unused and therefore wasted in many uses of the device. Excessive amounts of interconnection resources take up space on the device that could be used for additional logic or that could be eliminated in order to reduce the size and cost of the device.
Optimizing the amounts and configurations of the local interconnection resources can be especially important because these resources are replicated so many times on the device and because they are typically provided with high densities of programmable interconnections. For example, full populations of programmable interconnections may be provided between the local conductors associated with each region of programmable logic and the inputs to the subregions of that region. This makes any unnecessary excess in the number of local conductors or other local interconnection capacity extremely costly and undesirable for the device design as a whole.
In view of the foregoing, it is an object of this invention to provide improved organizations for the interconnection resources of programmable logic devices.
It is a more particular object of this invention to improve the organization of the interconnection resources at the local level in programmable logic devices of the general type shown in the above-mentioned Cliff et al. reference.